? semiconductor components industries, llc, 2008 september, 2008 ? rev. 1 1 publication order number: NB4N527SMNEVB/d NB4N527SMNEVB evaluation board manual for nb4n527s introduction on semiconductor has developed an evaluation board for the nb4n527s device as a convenience for the customers interested in performing their own device engineering assessment. this board provides a high bandwidth 50 controlled impedance environment. the pictures in figure 1 show the top and bottom view of the evaluation board, which can be configured in several different ways. this evaluation board manual contains: ? information on 16 ? lead qfn evaluation board ? assembly instructions ? appropriate lab setup ? bill of materials this manual should be used in conjunction with the nb4n527s device data sheet, which contains full technical details on the device specifications and operation. board lay ? up the 16 ? lead qfn evaluation board is implemented in four layers with split (dual) power supplies (figure 2, evaluation board lay ? up). for standard lab setup, a split (dual) power supply is essential to enable the 50 internal impedance in the oscilloscope as a device termination. the first layer or primary trace layer is 0.005 , thick rogers ro6002 material, which is designed to have equal electrical length on all signal traces from the device under the test (dut) to the sense output. the second layer is the 1.0 oz. copper ground plane. the fr4 dielectric material is placed between the second and third layer, and between the third and fourth layer. the third layer is also a 1.0 oz copper ground plane. the fourth layer is the secondary trace layer. top view bottom view figure 1. top and bottom view of the 16 qfn evaluation board http://onsemi.com evaluation board manual
NB4N527SMNEVB http://onsemi.com 2 figure 2. evaluation board lay ? up connecting power and ground planes top side of the evaluation board has the four surfaces mount test point clips labeled v cc , v ee , sma_gnd, and dut_gnd. dut_gnd is connected to the exposed flag of the qfn package. for proper operation, the exposed flag is recommended to be electrically left floating or tied to v ee , but must be thermally connected to a sufficient heat conduit such as a thermal plane exact supply voltage values that need to be applied can be found in table 1 and figures 4 and 5. table 1. power supply levels power supply span v cc v ee sma_gnd dut_gnd 3.0 v 1.75 v ? 1.25 v 0 v float or v ee 3.3 v 2.05 v ? 1.25 v 0 v float or v ee 3.6 v 2.35 v ? 1.25 v 0 v float or v ee stimulus (generator) termination all ecl outputs need to be terminated to v tt (v tt = v cc ?2.0 v = gnd) via a 50 resistor. the current board design utilizes the internal resistors and the v tdx pins are wired to ground. (more information on termination is provided in an8020). if evaluation does not require use of internal termination resistors, 0402 chip resistor pads are provided on the bottom side of the evaluation board. the jumper wires of the v tdx pin pads should be removed (j1, j4, j13 and j15 to sma_gnd jumper). solder the chip resistors to the bottom side of the board between the appropriate input of the device pin pads and the ground pads (for split power supply setup). likewise for cml outputs, cml stimulus signal need to be terminated to v cc via a 50 resistor. if internal resistors are used, the v tdx pin pads should be wired to v cc . to accomplish this configuration, the jumper wire has to be moved from sma_gnd ring to v cc ring on the bottom of the board. for the lvds configuration, v tdx pin pads of the d0 or d1 input has to be shorted to form 100 across dif ferential lines. this configuration is accomplished by moving the jumper wire from sma_gnd ring to complementary v tdx pin pad (example: vtd0 and vtd0b for d0 input and vtd1 and vtd1b for d1 input). dut termination for standard lab setup and test, a split (dual) power supply is required enabling the 50 internal impedance in the oscilloscope to be used as a termination of the signals (in split power supply setup sma_gnd is the system ground, v cc is varied, and v ee is ?1.25 v; see table 1, power supply levels). board components configuration the NB4N527SMNEVB evaluation board requires eight side sma connectors. placement locations are described in table 2 and figure 3. table 2. sma connectors and jumpers placement device j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 j13 j14 j15 j16 pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 connector no yes yes no no no no no yes yes yes no no yes yes no wire sma_gnd no no sma_gnd v ee no no v cc no no no no sma_gnd no no sma_gnd
NB4N527SMNEVB http://onsemi.com 3 ?? ?? ?? ?? j14 j15 j16 j1 j2 j3 j4 j5 j6 j7 j8 j9 j10 j11 j12 j13 d u t 4 x surface mount test points 2 x 10 f decoupling capacitors on the back of the pcb (c4, c2) 8 x sma connectors top view sma_gnd vcc vee pin 1 pad wire dut_gnd sma_gnd 4 x 0.01 f or 0.1 f decoupling capacitors (c1, c3, c5, c6) bottom view figure 3. components placement c4 c2
NB4N527SMNEVB http://onsemi.com 4 figure 4. lab setup for nb4n527s do do qo qo q1 q1 connect output of the generator to the input pins labeled j2, j3, j14, j15 (d0/d0b, d1/d1b) note: internal termination pins are connected to the sma gnd on the pcb. d1 d1 connect outputs of the device labeled j9, j10, j11 and j12 (q0/q0b, q1/q1b) directly to the scope head. power supply vcc gnd vee d u t differential signal generator test measuring equipment channel 1 channel 2 trigger trigger out out figure 5. simplified equipment lab setup block diagram 1. connect appropriate power supplies to v cc , v ee , sma_gnd, and sma_dut. 2. connect a signal generator to the input sma connectors. setup input signal according to the device data sheet. 3. connect a test measurement device on the device output sma connectors. note: the test measurement device must contain 50 termination.
NB4N527SMNEVB http://onsemi.com 5 table 3. bill of materials components manufacturer description part number qty. web site sma connector johnson* rosenberger sma connector, side launch, gold plated 142 ? 0701 ? 851 32k243 ? 40me3 8 http://www.johnsoncomponents.com http://www.rosenbergerna.com surface mount test points keystone* smt miniature test point 5015 4 http://www.keyelco.com chip capacitor avc corporation* 0603 0.01 f 10% 10 f 10% 06035c103kat2a t491c106k016as 4 2 http://www.avxcorp.com chip resistor panasonic* 0402 50 1% presicion thick film chip resistor erj ? 2rkf49r9x optional** http://www.panasonic.com evaluation board on semiconductor qfn 16 evaluation board eclqfn16evb 1 http://www.onsemi.com device samples on semiconductor qfn 16 package device nb4n527smn 1 http://www.onsemi.com *components are available through most distributors, i.e. www.newark.com, www.digikey.com
NB4N527SMNEVB http://onsemi.com 6 top layer second layer (sma_gnd plane) figure 6. gerber files
NB4N527SMNEVB http://onsemi.com 7 third layer (dut_gnd trace) bottom layer figure 7. gerber files
NB4N527SMNEVB http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NB4N527SMNEVB/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
